1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a memory device compatible with a static random access memory SRAM), which employs dynamic random memory (DRAM) cells, and a method of driving the SRAM-compatible memory.
2. Description of the Related Art
In general, random access memory (RAM) devices are classified into static RAM (SRAM) devices and dynamic RAM (DRAM) devices. A typical RAM includes a memory array composed of a plurality of unit memory cells arranged in a matrix form defined by rows and columns, and peripheral circuits adapted to control the input/output of data to/from the unit memory cells. Each of the unit memory cells of an SRAM stores one bit of data and is implemented by use of four transistors that form a latch structure and two transistors that act as transmission gates. Since a general SRAM stores data in unit memory cells each having a latch structure, a refresh operation is not required to maintain stored data. Furthermore, the SRAM devices have the advantages of rapid operating speed and low power consumption compared to the DRAM devices.
However, since each unit memory cell of an SRAM is composed of six transistors, the SRAM is disadvantageous in that it requires a large wafer area compared to a DRAM in which each unit memory cell is implemented using a transistor and a capacitor. In more detail, to manufacture a semiconductor memory device of the same capacity, the SRAM requires a wafer about six to ten times larger than that of the DRAM. The necessity of such a large wafer increases the unit cost of the SRAM. When a DRAM, instead of an SRAM, is used to reduce the cost, a DRAM controller is additionally required to perform a periodic refresh operation. Furthermore, the entire performance of a system is deteriorated due to the time required to perform the refresh operation and a slow operating speed.
In order to overcome the disadvantages of the DRAM and the SRAM, attempts have been made to implement an SRAM using DRAM cells. One of these attempts is the technology of effectively hiding a refresh operation from the outside, thus making the memory compatible with the SRAM.
For a write access operation in the conventional SRAM-compatible memory technology, there have been developments such as a method of internally securing a separate refresh period in a write access operation period, or delaying write access timing so as to secure the time required for the refresh of the DRAM cells of a memory array.
However, in the conventional SRAM-compatible memory technology, access timing for a write operation is delayed, so that a problem arises in that the overall operating speed of the SRAM-compatible memory is reduced.